Dipartimento di Fisica

RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades
JINST 20 (2025) P03024
DOI: 10.1088/1748-0221/20/03/P03024

Diamond-based sensors for in vitro cellular radiobiology: simultaneous detection of cell exocytic activity and ionizing radiation
Biosensors and Bioelectronics 220 (2023) 114876
DOI: 10.1016/j.bios.2022.114876

Comparative evaluation of analogue front-end designs for the CMS Inner Tracker at the High Luminosity LHC
JINST 16 (2021) P12014
DOI: 10.1088/1748-0221/16/12/P12014   Scopus: 2-s2.0-85122892110

Test results and prospects for RD53A, a large scale 65 nm CMOS chip for pixel readout at the HL-LHC
NIM A 936 (2019) 282-285
DOI: 10.1016/j.nima.2018.11.107   Scopus: 2-s2.0-85058715719   WOS: 000471828100103

RD53 analog front-end processors for the ATLAS and CMS experiments at the high-luminosity LHC
PoS (VERTEX2019) 021. Paper acknowledging Progetto Dipartimento di Eccellenza
DOI: 10.22323/1.373.0021   Scopus: 2-s2.0-85091656281

RD53A: A large scale prototype for HL-LHC silicon pixel detector phase 2 upgrades
PoS (TWEPP2018) 157
DOI: 10.22323/1.343.0157   Scopus: 2-s2.0-85072863891

Design implementation and test results of the RD53A, a 65 nm large scale chip for next generation pixel detectors at the HL-LHC
IEEE NSS/MIC (2018) Conference Proceeding
DOI: 10.1109/NSSMIC.2018.8824486   Scopus: 2-s2.0-85073095165   WOS: 000601256000220

Development of a Large Pixel Chip Demonstrator in RD53 for ATLAS and CMS Upgrades
PoS (TWEPP2017) 005
DOI: 10.22323/1.313.0005   Scopus: 2-s2.0-85050460911   WOS: 000455836200312

A Rad-Hard 12-bit Auto-Calibrated ADC in CMOS 65nm
IEEE NSS/MIC (2017) Conference Proceeding
DOI: 10.1109/NSSMIC.2017.8532904   Scopus: 2-s2.0-85058450453   WOS: 000455836200312

Results from CHIPIX-FE0, a Small-Scale Prototype of a New-Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC
PoS (TWEPP2017) 024
DOI: 10.22323/1.313.0024   Scopus: 2-s2.0-85050474107

First measurements of a prototype of a new generation pixel readout ASIC in 65 nm CMOS for extreme rate HEP detectors at HL-LHC
IEEE NSS/MIC (2016) Conference Proceeding
DOI: 10.1109/NSSMIC.2016.8069857   Scopus: 2-s2.0-85041700283   WOS: 000432419500479

New Development on Digital Architecture for Efficient Pixel Readout ASIC at Extreme Hit Rate for HEP Detectors at HL-LHC
IEEE NSS/MIC (2016) Conference Proceeding
DOI: 10.1109/NSSMIC.2016.8069855   Scopus: 2-s2.0-85041701881   WOS: 000432419500477

TOFPET 2: a high-performance ASIC for time and amplitude measurements of SiPM signals in time-of-flight applications
JINST 11 (2016) C03042
DOI: 10.1088/1748-0221/11/03/C03042   Scopus: 2-s2.0-84965006999   WOS: 000375408700067

A prototype of a new generation readout ASIC in 65 nm CMOS for pixel detectors at HL-LHC
PoS (VERTEX2016) 054
DOI: 10.22323/1.287.0054   Scopus: 2-s2.0-85041726015

Pixel front-end with synchronous discriminator and fast charge measurement for the upgrades of HL-LHC experiments
JINST 11 (2016) C03013
DOI: 10.1088/1748-0221/11/03/C03013   Scopus: 2-s2.0-84961992263   WOS: 000375746200014

Design of a 10-bit segmented current-steering digital-to-analog converter in CMOS 65 nm technology for the bias of new generation readout chips in high radiation environment
JINST 11 (2016) C01027
DOI: 10.1088/1748-0221/11/01/C01027   Scopus: 2-s2.0-84957023150   WOS: 000371469800027

A Low-Power Low-Noise Synchronous Pixel Front-End Chain in 65 nm CMOS Technology with Local Fast ToT Encoding and Autozeroing for Extreme Rate and Radiation at HL-LHC
IEEE NSS/MIC (2015) Conference Proceeding
DOI: 10.1109/NSSMIC.2015.7581969   Scopus: 2-s2.0-84994068527   WOS: 000413680600251

Description and performance of track and primary-vertex reconstruction with the CMS tracker
JINST 9 (2014) P10009
DOI: 10.1088/1748-0221/9/10/P10009   Scopus: 2-s2.0-84908341975   WOS: 000345858500052

Radiation tolerance of a moderate resistivity substrate in a modern CMOS process
NIM A 718 (2013) 347-349
DOI: 10.1016/j.nima.2012.10.020   Scopus: 2-s2.0-84887815730   WOS: 000320596900112

• Fisica sperimentale delle alte energie presso l'esperimento Compact Muon Solenoid (CMS) al Large Hadron Collider (LHC) del CERN di Ginevra.
• Tecniche sperimentali per rivelatori di radiazione.
• Rivelatori al silicio per il tracciamento di particelle.
• Elettronica di lettura per rivelatori di particelle.
• Progettazione CAD di circuiti integrati dedicati di tipo Application Specific Integrated Circuits (ASIC) in tecnologie CMOS ad altissima densità di integrazione (VLSI).
• Progettazione del nuovo chip di lettura in tecnologia CMOS 65nm per l'upgrade del rivelatore a pixel dell'esperimento CMS per la fase ad altissima luminosità di LHC (High-Luminosity LHC, HL-LHC).
• Programmazione di dispositivi di tipo Field Programmable Gate Array (FPGA) per la realizzazione di sistemi di acquisizione dati (DAQ).